–coherent modulation is getting a lot of traction.”
Brig Asay, director of strategic plan-
ning—Internet Infrastructure Group, at Keysight Technologies: “We expect that 2019 will be the year of the fifth generation as PCIExpress, and DDR will both be roll- ing into their fifth-generation technologies. As PCIExpress moves to Gen5, its recent competitors—CCIX, GenZ, OPENCapi, etc.—will all need to gain market share and show their value to stay in consideration. It is no longer viable from them to just be >30 Gbps, but they must show that they have value outside of speed alone. We expect that virtual reality and augmented real- ity will continue to gain traction, pushing display technologies to new generatwions. We also see the beginning of the conver- gence of buses that are using type-C con- nectors such as USB and DisplayPort.” Patrick Connally, product manager
at Teledyne LeCroy: “The electronics industry’s ongoing shift to the next gen- eration of high-speed communication buses (such as PCIe Gen5) gives rise to the challenges of sending faster signals over relatively lossy channels. As 2019 approaches, current high-speed specifi- cations are looking to double their speed or bandwidth while also trying to re- duce power consumption. Tis, in turn, makes design margins smaller and test requirements more complex. Tis trend manifests in communications standards through requirements such as dynamic
link training, in which the interactions between the physical and protocol layers become increasingly important.” “Te drive for lower power consump-
tion in many devices and systems means lower power-rail voltages, which in turn means that those rails can tolerate very little noise before they infringe on high- speed data transmission. Thus, power- integrity (PI) analysis is of increasing im- portance in high-speed systems.” Hiroshi Goto, business develop-
ment manager at Anritsu: “Data traf- fic volumes are expected to increase due to the spread of next-generation 5G mobile communications and cloud services. To cope with this demand, infrastructure operators, such as data centers, are investigating not only speed increases, but also PAM4 and multilane communications methods.” “400GbE speeds are being deployed
using either the 26.5625-Gbaud PAM4 x 8 lanes or 53.125- Gbaud PAM4 x 4 lanes methods. When using the PAM4 method expressing data as four amplitude lev- els, the gap between signal levels is one- third that of the NRZ method, which re- duces the unit time per symbol at higher baud rates, emphasizing the importance of signal quality in achieving high-speed transmissions. On the other hand, the inability to avoid degraded signal qual- ity caused by crosstalk and noise result- ing from use of multiple lanes and high- density circuit design increases the need for evaluation of minimum Rx sensitivity using stress-test signals.”
At DesignCon Tese trends and the vendors providing high-speed digital test equipment will be on display at DesignCon, held Jan. 29-31 in Santa Clara, CA. Now in its 24th year, DesignCon brings together nearly 5,000 professionals in the high-speed com- munications and semiconductor com- munities for three days of education and networking activities, and brands itself as the largest U.S. event for chip, board, and system designers. Rohde & Schwarz will be on-hand at
DesignCon to feature their latest VNA, phase noise analyzer, and oscilloscope so- lutions for signal integrity measurements. These solutions cover specifications in- cluding high frequency multiport cross- talk—which the company promotes as the first multiport VNA offering up to 24 inte- grated test ports—PAM4, PCIe clock jitter, de-embedding, and high-speed PCB prob- ing. Power rail probes will also be in the Rohde & Schwarz booth, displaying power integrity measurements. Rohde & Schwarz will also run a series of seminars on de-em- bedding, signal integrity, power integrity, power rail sequencing probing, clock jitter measurements, characterization of signal integrity using VNAs, and crosstalk. At booth No. 615, Anritsu will debut
its 64-Gbaud PAM4 Pulse Pattern Gen- erator (PPG) and 32-Gbaud PAM4 Er- ror Detector (ED) modules, supporting 400GbE and Over 400G bit error rate (BER) tests for its Signal Quality Analyzer- R MP1900A BERT. Anritsu said with the modules installed, the MP1900A provides engineers with best-in-class signal quality and excellent Rx sensitivity to more accu- rately verify performance of 400GbE opti- cal modules and devices being designed for high-speed communications systems. Asay said Keysight plans to show it is
S Rohde & Schwarz said its ZNBT is the only true multiport VNA with up to 24 ports.
X Keysight’s N1930B Physical Layer Test System 2018 Software, which has been updated and will be displayed at DesignCon.
up-to-date in the latest trends in VNA/ PCE solutions and DDR, while also show- ing it is future-ready by demonstrating its latest real-time oscilloscope introduction and its 110 GHz of bandwidth. “We will demonstrate the merging of customer workflows and the need for data that can be compared from design/simula- tion through validation through manu- facturing with our DDR4 software solu- tion, which fully merges our validation
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