HIGH-SPE ED DIGITAL TEST


Sponsored by


W Rohde & Schwarz’ new FSWP phase noise analyzer offers the func- tionality needed to test low-jitter clocks in both SSC OFF mode and SSC ON mode.


SPECIAL REPORT RT


PAM4, PCIE, JITTER LIMITS MOVE THE NEEDLE IN HIGH-SPEED DIGITAL


By Mike Hockett, Editor-in-Chief


While high-speed digital design engineers continuously combat de-


mands for products and systems that are lower power, lower cost, more reli- able, user-friendly, mobile, and faster than ever, test engineers are challenged to determine if shown defects are rooted in the design, or in the equipment being used to test them. Being a good test engineer means


taking the proper steps to ensure errors caused by things such as bad connec- tions, worn-out cables, and human er- ror are systematically eliminated. It also means ensuring uncertainties caused by test equipment are accounted for. Tight budgets may make ‘just good


enough’ equipment appealing to test engineers, but that increases the likeli- hood of illegitimate test results. Thus, these engineers are also tasked with keeping up with the latest develop- ments in high-speed digital test equip- ment and using cutting-edge instru- ments that keep up with the pace of technological developments.


6 EVALUATION ENGINEERING JANUARY 2019


Trending Data rates will only speed up in 2019, with that key factor leading trends in high-speed digital test. We at Evalua- tion Engineering asked a number of test equipment vendors about what they’re seeing as trends in this space. Here’s what they had to say. Faride Akretch, marketing manager


for Rohde & Schwarz: “Tere are several trends that we see, and they are all relat- ed to the increasing speed of clocks and data and all have different implications on how to test. 1. As the data rates in high-speed digi- tal designs increase, the limits for overall system jitter become tighter. This especially applies to the vari- ous components of the clock tree, where the jitter limits for reference clocks, clock buffers, and jitter at- tenuators are even tighter. Here, the trend is to increasingly use phase noise analyzers.


2. In regard to the signal-integrity as- pect of high-speed digital designs


and the components used, vec- tor network analyzers (VNA) are increasingly replacing traditional time domain reflectometry (TDR) setups for testing passive compo- nents such as connectors, cables, and PCBs. Users benefit from the higher accuracy, speed, and ESD robustness of the VNA, making the VNA the instrument of choice in this field.


3. And thirdly, with more and more radios, components, and complex sub-systems all part of a design, we do see a trend towards multiport in- struments, where many interdepen- dencies can be tested at once.”


Keyur Diwan, group product mar-


keting manager for Tektronix: “To keep pace with data center communication needs at 400G and enable new applica- tions, the PCIe 5.0 specification is in de- velopment, which will increase through- put to 32 GT/s, while also meeting more demanding requirements for low latency and power efficiency. Other trends include: • Te shift to cloud services is driving the need for ever larger networks for the cloud providers. 400Gb/s for DCI and metro networks will soon be commercially available.


• Coming technology transitions of >400G/600G will drive new technologies to overcome cur- rent physical limitations of direct detect links. The new standard for baud rates >400G is 400G ZR


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