Designs are first created function-


ally, without concern for timing, with initial simulation verifying that the project and input/output functions work as intended. Once functionality is achieved, cycle-accurate simulation is used to verify speed or other criti-


cal parameters. Te final step is synthesis, requiring verification of timing constraints for the FPGA’s I/Os and internal logic. Once verified, the FPGA can be programmed and the design verified with the hardware. As shown in Figure 2, the FPGA design


and deployment process can employ both vendor-specific and vendor-neutral tools.


For the design block, the use of vendor- neutral tools, specifically HDL (either VHDL or Verilog) is highly desirable. VHDL and Verilog are open tools and are widely accepted standards. And since these are vendor neutral tools, design portability can be maximized, minimizing vendor “lock- in” to a specific FPGA brand or module as well as mitigating dependence on one sup- plier/vendor. In addition, these tools are supported by IEEE standards for common HDL languages: 1076-2008—IEEE Stan- dard VHDL Language Reference Manual and 1364-2005—IEEE Standard for Verilog Hardware Description Language.


“With the ability to design and program an instrument for specific applications, test engineers have the flexibility to support not only a current product, but also future products that might require a specialized instrument or interface.” — Mike Dewey, Marvin Test Solutions


Function/Bus Interface A/D and D/A converters MIL-STD 1553 ARINC 429 RS-232 RS-422/RS-485 CAN Bus Ethernet USB I2C, SPI SpaceWire SerDes Camera Link Physical Interface/Characteristics


High resolution and high speed converters for analog measurement/stimulus applications


Tri-axial, transformer coupled, 18 -26 Vpp output Differential, high voltage Unbalanced, bi-polar Balanced, bi-polar Differential, CAN bus specific XCVR Differential, transformer coupled Differential, logic levels Buffered, logic levels LVDS LVDS LVDS Serial Front Panel Data Port (FPDP) Copper/Fiber JANUARY 2019 EVALUATIONENGINEERING.COM 19


WTable 1. Examples of physical interfaces that might be supported by an external FPGA interface.


TFigure 3. PXIe FPGA module with daughter board


To facilitate the design/deployment


process as well as maximize supportabil- ity and life-cycle management of a user- programmable FPGA instrument, test engineers should consider adopting the following guidelines when selecting and deploying these instruments: • Use HDL where possible. HDL is sup- ported by all major FPGA vendors’ tools and does not require any propri- etary software or support. In addition, thorough documentation of HDL al- lows code to be ported and/or modi- fied for use in various designs, and for support of HDL designs across orga- nizations, functions, and time.


• If design entry employs some other method (e.g., schematic or graphi- cal), the output should be HDL, which can be read and modified.


• Designers should use FPGA ven- dor-specific design tools (e.g., Xilinx ISE/Vivado, Altera Quartus). While not vendor-neutral, these vendor-specific tools provide com- prehensive support for new and legacy FPGAs.


In addition, these


tools support the complete FPGA design flow from HDL entry to FPGA binary file generation.


Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32